1. Field of the Invention
The present invention relates to a semiconductor memory device with a rapid access mode.
2. Description of the Related Art
Recently, as the processing speed of microprocessors and the like is increased, the access speed of a semiconductor memory device is also required to be increased. In order to increase the access speed of the semiconductor memory device, it is also necessary to increase the access speed in random access. In some cases, by special access modes such as a burst mode and a page mode, the access speed is attempted to be increased so as to exceed the access speed in random access.
FIG. 6 shows a construction of a read only memory (ROM) with a general page mode.
In this ROM, a number of bit lines B are formed along a vertical direction of the figure, and a number of row select lines WL are formed along a horizontal direction of the figure so as to cross the bit lines B. To each of the crossings of the bit lines B and the row select lines WL, a memory cell 21 is connected. FIG. 6 only shows one row select line WL.sub.j and (k+1) bit lines B.sub.i0 -B.sub.ik which are sequentially made readable in the page mode.
Each memory cell 21 is constructed so as to ground the adjacent bit line B via a MOS transistor Q.sub.M. A gate terminal of the MOS transistor Q.sub.M is connected to the adjacent row select line WL. Accordingly, drain terminals of the MOS transistors Q.sub.M of the memory cells 21 arranged in one column are connected to one and the same bit line B. Also, gate terminals of the MOS transistors Q.sub.M of the memory cells 21 arranged in one row are connected to one and the same row select line WL. FIG. 6 only shows (k+1) memory cells 21 connected to the respective crossings of the row select line WL.sub.j and the (k+1) bit lines B.sub.i0 -B.sub.ik, and MOS transistors Q.sub.Mij0 -Q.sub.Mijk corresponding to these memory cells 21.
A transistor Q.sub.M of each memory cell 21 is formed in the following manner: When the memory cell 21 stores the logical state of "0", a threshold value V.sub.TH of the transistor Q.sub.M is the same as that in the usual enhancement type. When the memory cell 21 stores the logical state of "1", the threshold value V.sub.TH is equal to or larger than the source voltage. Accordingly, any one of the row select lines WL is made to be a high level, among the memory cells 21 connected to the high-level row select line WL, transistors Q.sub.M of memory cells 21 which store the logical state of "0" are turned ON, and transistors Q.sub.M of the other memory cells 21 remain in the OFF state (normal OFF).
The above-mentioned bit lines B are connected to respective input terminals of sense amplifiers 22 via corresponding MOS transistors Q.sub.C. Gate terminals of the MOS transistors Q.sub.C are connected to a column select line C. When the column select line C is made to be a high level, the MOS transistors Q.sub.C are turned ON. Each group of (k+1) M0S transistors Q.sub.C is connected to one and the same column select line C. In FIG. 6, (k+1) MOS transistors Q.sub.Ci0 -Q.sub.Cik connected to the (k+1) bit lines B.sub.i0 -B.sub.ik are commonly connected to one column select line C.sub.i.
Each sense amplifier 22 validates a logical level depending on the potential of the corresponding bit line B, and outputs the valid logical level. The bit lines B.sub.i0 -B.sub.ik are connected to (k+1) sense amplifiers 22 via the MOS transistors Q.sub.Ci0 -Q.sub.Cik, respectively. It is understood that a number of bit lines B are also connected to these sense amplifiers 22 via other MOS transistors Q.sub.C which are not shown.
Output terminals of the sense amplifiers 22 are connected to an input terminal of an output buffer 23 via respective MOS transistors Q.sub.P. Data select lines P are connected to gate terminals of the MOS transistors Q.sub.P. When the data select lines P are made to be a high level, the MOS transistors Q.sub.P are turned ON. As to the data select lines P, (k+1) data select lines P.sub.0 -P.sub.k constitute one set. The data select lines P.sub.0 -P.sub.k in one set are respectively connected to gate terminals of (k+1) MOS transistors Q.sub.P which constitute one set. In FIG. 6, the output terminals of the (k+1) sense amplifiers 22 are connected to the input terminal of one output buffer 23 via the (k+1) MOS transistors Q.sub.P0 -Q.sub.Pk in one set.
The operation of the ROM having the aboveconstruction will be described with reference to FIG. 7.
When an address signal is made valid at time t11, high-order bits of an address signal are decoded, so that one of row select lines WL and one of column select lines C are made high. Now consider the case where the row select line WL.sub.j and the column select line C.sub.i shown in FIG. 6 are made high. In the memory cells 21 storing the logical state of "0" among the memory cells 21 connected to the row select line WL.sub.j, corresponding MOS transistors Q.sub.M are turned ON. Accordingly, the potentials of the bit lines B connected to the memory cells 21 are grounded so as to gradually change to the low level. The MOS transistors Q.sub.M of the other memory cells 21 remain in the OFF state, so that the potentials of the bit lines B connected to these memory cells 21 gradually change to the high level. In addition, since the column selection line C.sub.i is at the high level, the MOS transistors Q.sub.Ci0 -Q.sub.Cik are all in the ON state. Accordingly, the potentials of the bit lines B.sub.i0 -B.sub.ik connected to the MOS transistors Q.sub.Ci0 -Q.sub.Cik are input into the sense amplifiers 22, respectively. The sense amplifiers 22 amplify weak potentials of low or high level of the respective bit lines B.sub.i0 -B.sub.ik, and output valid logical levels S.sub.i0 -S.sub.ik. However, the sense amplifiers 22 require a certain time for amplifying the weak potentials so as to validate the logical levels S.sub.i0 -S.sub.ik.
At time t11, low-order bits of the address signal are also decoded, so that one of the (k+1) data select lines P.sub.0 -P.sub.k is set to be a high level. Now consider the case where the data select line P.sub.0 is made high as shown in FIG. 7. The MOS transistor Q.sub.P0 connected to the data select line P.sub.0 is turned ON, so that only the logical level Si.sub.0 of the sense amplifier 22 which is obtained by amplifying the potential of the bit line B.sub.i0 is output via the output buffer 23 at time t12. As described above, the usual access mode which is the normal access mode requires a time period TN from the validation of the address signal at time t11 to the output of the data of logical level S.sub.i0 from the output buffer 23 at time t12. The time period TN is relatively long because the time period TN includes the time required for the validation of logical level by the sense amplifier 22.
However, at time t12, the remaining k sense amplifiers 22 also finish validating the logical levels S.sub.i1 -S.sub.ik of the bit lines B.sub.i1 -B.sub.ik. Due to this fact, when only the low-order bits of the address signal are changed so as to sequentially set the data select lines P.sub.1 -P.sub.k to be a high level, the output buffer 23 outputs the data of logical level S.sub.i1 at time t13 after the data select line P.sub.1 is set to be a high level, and outputs data of logical level S.sub.i2 at time t14, and so on. In this way, it is possible to sequentially output the data of logical levels at a time interval of T.sub.P until the data of logical level S.sub.ik is output. The time interval T.sub.P is extremely short because it is not necessary for the sense amplifiers 22 to validate the logical levels. As a result, a rapid access can be realized.
As described above, the ROM shown in FIG. 6 operates in the usual or normal access mode in the first access. However, if the access is continuously performed to the succeeding addresses, it is possible to perform the rapid access in the page mode for the succeeding k addresses at the most. It is understood that such an increase of the access speed can also be realized in other semiconductor memory devices such as an erasable and programmable ROM (EPROM) and a dynamic random access memory (DRAM), in addition to the ROM.
However, when the rapid access in the page mode is performed in the ROM or the like, it is necessary for the microprocessor and the like to check as to whether the sequentially specified address is included in the same page range of (k+1) addresses, and if necessary to change the access mode depending on the checked result. Such check and mode change complicate the access process for the semiconductor memory device. As a countermeasure against the complicated access process, one method is conventionally proposed. In the proposed method, if it is necessary to switch the rapid access mode to the usual access mode, the semiconductor memory device informs the microprocessor and the like of the switching necessity, and the microprocessor and the like automatically waits during the change of the access mode. Specifically, at the 1989 IEEE International Solid-State Circuits Conference (ISSCC), there was an announcement as to an EPROM in which a miss (non-local) signal MISS is output when the access mode is to be changed from the burst mode to the usual access mode.
FIG. 8 shows the construction of a conventional EPROM. The EPROM includes a memory array 1 with memory cells having an organization of 64K.times.16 bits. The twelve high-order bits of the address signal A.sub.4 -A.sub.15 among sixteen bits of the address signal A.sub.0 -A.sub.15 are input into an X decoder 3 via a first address input circuit 2 and a first latch circuit 10. As a result, the memory cells in the memory array 1 are accessed. Specifically, the high-order bits of the address signal A.sub.4 -A.sub.15 are input to the first latch circuit 10 via the first address input circuit 2. A chip select signal CS is in a low-level (active) state. In the above condition, at the timing of the falling edge (when becoming active) of an address strobe signal AS, the high-order bits of the address signal A.sub.4 -A.sub.15 are latched by the latch circuit 10. Then, the high-order bits of the address signal A.sub.4 -A.sub.15 are fed from the latch circuit 10 to the X decoder 3, so that 256 memory cells in the memory array 1 are selected and the 256 bits of data thereof are simultaneously read out. A logical circuit 15 is used for gating the address strobe signal AS in accordance with the chip select signal CS.
As to the 256 bits of data read out from the memory array 1, respective logical levels are validated respectively by 256 sense amplifiers in a sense amplifier circuit 5. The data of valid logical levels are output to a multiplexer 6 via line buffers in the sense amplifier circuit 5. The four low-order bits of the address signal A.sub.0 -A.sub.3 are input to the multiplexer 6 via a second address input circuit 8. Then, depending on the value of the address signal of the low-order bits A.sub.0 -A.sub.3 (one of 16 values), the data of 16 bits are selected from the 256 bits (16.times.16 bits) of data. The selected 16 bits of data are output to an output circuit 7. When both of the chip select signal CS and an output enable signal OE are at the low level (active), the output circuit 7 outputs the 16 bits of data which are fed from the multiplexer 6 to data buses and the like as data D.sub.0 -D.sub.15 of 1 word. A logical circuit 13 is used for gating the output enable signal OE in accordance with the chip select signal CS, and converts the signal into a signal in a positive logic which is in turn output.
Accordingly, in the EPROM, the logical levels of the 256 bits of data are made valid by the sense amplifier circuit 5 in the first access. Thereafter, by changing only four low-order bits of the address signal A.sub.0 to A.sub.3, it is possible to perform the rapid access to the succeeding sixteen 16-bit data.
The twelve high-order bits of the address signal A.sub.4 -A.sub.15 which are latched in the first latch circuit 10 are also fed to a second latch circuit 11. In the low level (active) condition of the chip select signal CS, the second latch circuit 11 latches the high-order bits of the address signal A.sub.4 -A.sub.15 at the timing of the rising edge (when returning to be inactive) of the address strobe signal AS. The high-order bits of the address signal A.sub.4 -A.sub.15 latched in the second latch circuit 11 are fed to a comparator circuit 12 together with the high-order bits of the address signal A.sub.4 -A.sub.15 which are input via the first address input circuit 2 at that time. The comparator circuit 12 outputs a low level when the sets of high-order bits of the address signals A.sub.4 -A.sub.15 do not match with each other. The comparator circuit 12 outputs a miss signal MISS which becomes a low level (active) when the low level is output from the comparator circuit 12, to the outside via a logical circuit 14. The logical circuit 14 is used for gating the output of the comparator circuit 12 in accordance with the chip select signal CS. Both the output of the logical circuit 15 and the output of the comparator circuit 12 are fed to the sense amplifier circuit 5 via a logical circuit. Accordingly, the sense amplifier circuit 5 is made to operate only when both the chip select signal CS and the address strobe signal AS are at the low level (active) and the output of the comparator circuit 12 is at the low level, i.e., when the access is performed to the memory array 1 and the high-order bits of the address signals A.sub.4 -A.sub.15 do not match with each other.
The access operation of the EPROM having the above construction will be described with reference to FIGS. 9 and 10.
It is assumed that at time t20 in FIG. 9, both the chip select signal CS and the output enable signal OE are at a low level (active), and the high-order bits of the address signal A.sub.4 -A.sub.15 having a value of #N is input into the first address input circuit 2 and latched in the first latch circuit 10. When the address strobe signal AS is again made high (inactive) at time t21, the high-order bits of the address signal A.sub.4 -A.sub.15 of #N are latched in the second latch circuit 11.
Herein, as is shown in the figure, it is assumed that the high-order bits of the address signal A.sub.4 -A.sub.15 are changed to be a value of #M at time t22. The comparator circuit 12 detects the mismatch with the high-order bits of the address signal A.sub.4 -A.sub.15 (#N) latched in the second latch circuit 11, so as to output a low level. Thus, the miss signal MISS becomes low level (active). At time t23, the address strobe signal AS becomes low level (active), and the first latch circuit 10 latches the high-order bits of the address signal A.sub.4 -A.sub.15 which are then fed to the X decoder 3. At this time, the output of the logical circuit 16 is at the high level, so that the sense amplifier circuit 5 is driven. As a result, new 256 bits of data are read out from the memory array 1, and the logical levels thereof are made valid by the sense amplifier circuit 5. At time t24, the output circuit 7 outputs the 16-bit data D.sub.0 -D.sub.15 which are selected by the multiplexer 6 based on the low-order bits of the address signal A.sub.0 -A.sub.3 which are changed simultaneously with the high-order bits of the address signal A.sub.4 -A.sub.15. When the address strobe signal AS risers to a high level at time t25, the second latch circuit 11 latches the high-order bits of the address signal A.sub.4 -A.sub.15 having the value of #M. Therefore, the output of the comparator circuit 12 becomes high level, so that the miss signal MISS is also returned to the high level (inactive).
Therefore, in the case of FIG. 9, the access is performed in a usual access mode in which the sense amplifier circuit 5 makes the logical levels valid. The microprocessor and the like wait during The low level (active) period of the miss signal MISS. Thus, it is possible to surely read out the data D.sub.0 -D.sub.15 without considering the access mode.
Thereafter, if only the low-order bits of the address signal A.sub.0 -A.sub.3 are changed at time t26 as is shown in FIG. 10, the value of the high-order bits of the address signal A.sub.4 -A.sub.15 is not changed from #M. Thus, the output of the comparator circuit 12 remains at the high level, and the miss signal MISS also remains at the high level. However, the multiplexer 6 selects other data from the line buffers in the sense amplifier circuit 5 in accordance with the changed low-order bits of the address signal A.sub.0 -A.sub.3. Accordingly, at time t27 after the lapse of an extremely short time period, the output circuit 7 can output a new set of 16-bit data D.sub.0 -D.sub.15 which are selected by the multiplexer 6. Thereafter, if only the low-order bits of the address signal A.sub.0 -A.sub.3 are sequentially switched as is shown in the figure, the corresponding 16-bit data D.sub.0 -D.sub.15 can be read out at a high speed. Therefore, in the case of FIG. 10, the access is performed in a rapid access mode in which the sense amplifier 5 is not required to validate the logical levels, and the miss signal MISS maintains the high level (inactive). Thus, a microprocessor and the like can sequentially read out the output data D.sub.0 -D.sub.15 at a high speed without an excess waiting period.
As described above, in the EPROM shown in FIG. 8, the access mode can be automatically changed by monitoring the miss signal MISS. Accordingly, the EPROM shown in FIG. 8 has an advantage in that the load for the microprocessor and the like can be reduced during the rapid access mode. In another type of semiconductor memory device, the miss signal MISS can be output in the same way.
However, in the conventional device, in order to produce such a miss signal MISS, two latch circuits 10 and 11 for temporarily storing the multiple bits of the address signal A.sub.4 -A.sub.15 are required in addition to the comparator circuit 12. If the number of bits of the address signal are increased as the storing capacity of the semiconductor memory device is increased, it is necessary to increase the number of bits in the latch circuits 10 and 11. This results in a further increase of circuit scale.
The above-described conventional latch circuits 10 and 11 use the address strobe signal AS which asserts the validation of the address signal, in order to latch the high-order bits of the address signal A.sub.4 -A.sub.15. However, in the presently used semiconductor memory device, a non-synchronous or asynchronous system in which such an address strobe signal AS is not used is mainly used due to the convenience.
Accordingly, the conventional semiconductor memory device involves a problem in that, when a miss signal MISS is produced for conveniently using the rapid access mode, the chip area is increased because of the increase of circuit scale of the latch circuits 10 and 11. In addition, the conventional semiconductor memory device operates in a non-synchronous or asynchronous system in which the operation is performed by the input of the address signal without using the address strobe signal AS. Whereas, in order to produce the miss signal MISS, it is necessary to use the address strobe signal AS in a synchronous system. This significantly limits the range of use.